[Setting]
UnitSize=1
TotalUnitNum=23

[Item_0]
ItemUnitOffset=0
ItemUnitNum=4
ItemBitEnable=0
ItemDesc=Identifiers

[Item_1]
ItemUnitOffset=4
ItemUnitNum=2
ItemBitEnable=1
ItemDesc=Command Register

[Item_2]
ItemUnitOffset=6
ItemUnitNum=2
ItemBitEnable=2
ItemDesc=Device Status

[Item_3]
ItemUnitOffset=8
ItemUnitNum=1
ItemBitEnable=3
ItemDesc=Revision ID

[Item_4]
ItemUnitOffset=9
ItemUnitNum=3
ItemBitEnable=4
ItemDesc=Class Codes

[Item_5]
ItemUnitOffset=12
ItemUnitNum=1
ItemBitEnable=5
ItemDesc=Cache Line Size

[Item_6]
ItemUnitOffset=13
ItemUnitNum=1
ItemBitEnable=6
ItemDesc=Master Latency Timer

[Item_7]
ItemUnitOffset=14
ItemUnitNum=1
ItemBitEnable=7
ItemDesc=Header Type

[Item_8]
ItemUnitOffset=15
ItemUnitNum=1
ItemBitEnable=8
ItemDesc=Built In Self Test (Optional)

[Item_9]
ItemUnitOffset=16
ItemUnitNum=4
ItemBitEnable=9
ItemDesc=Memory Register Base Address, lower 32-bits <BAR0>

[Item_10]
ItemUnitOffset=20
ItemUnitNum=4
ItemBitEnable=10
ItemDesc=Memory Register Base Address, upper 32-bits <BAR1>

[Item_11]
ItemUnitOffset=24
ItemUnitNum=4
ItemBitEnable=11
ItemDesc=Index/Data Pair Register Base Address <BAR2> (Optional)

[Item_12]
ItemUnitOffset=28
ItemUnitNum=4
ItemBitEnable=12
ItemDesc=Reserved <BAR3>

[Item_13]
ItemUnitOffset=32
ItemUnitNum=4
ItemBitEnable=13
ItemDesc=Vendor Specific

[Item_14]
ItemUnitOffset=36
ItemUnitNum=4
ItemBitEnable=14
ItemDesc=Vendor Specific

[Item_15]
ItemUnitOffset=40
ItemUnitNum=4
ItemBitEnable=15
ItemDesc=CardBus CIS Pointer

[Item_16]
ItemUnitOffset=44
ItemUnitNum=4
ItemBitEnable=16
ItemDesc=Subsystem Identifiers

[Item_17]
ItemUnitOffset=48
ItemUnitNum=4
ItemBitEnable=17
ItemDesc=Expansion ROM Base Address (Optional)

[Item_18]
ItemUnitOffset=52
ItemUnitNum=1
ItemBitEnable=18
ItemDesc=Capabilities Pointer
ItemPointer=1

[Item_19]
ItemUnitOffset=53
ItemUnitNum=7
ItemBitEnable=19
ItemDesc=Reserved

[Item_20]
ItemUnitOffset=60
ItemUnitNum=2
ItemBitEnable=20
ItemDesc=Interrupt Information

[Item_21]
ItemUnitOffset=62
ItemUnitNum=1
ItemBitEnable=21
ItemDesc=Minimum Grant (Optional)

[Item_22]
ItemUnitOffset=63
ItemUnitNum=1
ItemBitEnable=22
ItemDesc=Maximum Latency (Optional)

[Item_23]
ItemUnitOffset=0
ItemUnitNum=1
ItemBitEnable=23
ItemDesc=PCI Power Management Capability ID
ItemPointerOffset=1

[Item_24]
ItemUnitOffset=1
ItemUnitNum=1
ItemBitEnable=24
ItemDesc=Capabilities Pointer
ItemPointerOffset=1 
ItemPointer=2

[Item_25]
ItemUnitOffset=2
ItemUnitNum=2
ItemBitEnable=25
ItemDesc=PCI Power Management Capabilities
ItemPointerOffset=1

[Item_26]
ItemUnitOffset=4
ItemUnitNum=2
ItemBitEnable=26
ItemDesc=PCI Power Management Control and Status
ItemPointerOffset=1

[Item_27]
ItemUnitOffset=0
ItemUnitNum=1
ItemBitEnable=27
ItemDesc=Message Signaled Interrupt Capability ID
ItemPointerOffset=2

[Item_28]
ItemUnitOffset=1
ItemUnitNum=1
ItemBitEnable=28
ItemDesc=Capabilities Pointer
ItemPointerOffset=2
ItemPointer=3

[Item_29]
ItemUnitOffset=2
ItemUnitNum=2
ItemBitEnable=29
ItemDesc=Message Signaled Interrupt Message Control
ItemPointerOffset=2

[Item_30]
ItemUnitOffset=4
ItemUnitNum=4
ItemBitEnable=30
ItemDesc=Message Signaled Interrupt Message Address
ItemPointerOffset=2

[Item_31]
ItemUnitOffset=8
ItemUnitNum=4
ItemBitEnable=31
ItemDesc=Message Signaled Interrupt Upper Address
ItemPointerOffset=2

[Item_32]
ItemUnitOffset=12
ItemUnitNum=2
ItemBitEnable=32
ItemDesc=Message Signaled Interrupt Message Data
ItemPointerOffset=2

[Item_33]
ItemUnitOffset=16
ItemUnitNum=4
ItemBitEnable=33
ItemDesc=Message Signaled Interrupt Mask Bits (Optional)
ItemPointerOffset=2

[Item_34]
ItemUnitOffset=20
ItemUnitNum=4
ItemBitEnable=34
ItemDesc=Message Signaled Interrupt Pending Bits (Optional)
ItemPointerOffset=2

[Item_35]
ItemUnitOffset=0
ItemUnitNum=1
ItemBitEnable=35
ItemDesc=MSI-X Capability ID
ItemPointerOffset=3

[Item_36]
ItemUnitOffset=1
ItemUnitNum=1
ItemBitEnable=36
ItemDesc=Capabilities Pointer
ItemPointerOffset=3
ItemPointer=4

[Item_37]
ItemUnitOffset=2
ItemUnitNum=2
ItemBitEnable=37
ItemDesc=MSI-X Message Control
ItemPointerOffset=3

[Item_38]
ItemUnitOffset=4
ItemUnitNum=4
ItemBitEnable=38
ItemDesc=MSI-X Table Offset and Table BIR
ItemPointerOffset=3

[Item_39]
ItemUnitOffset=8
ItemUnitNum=4
ItemBitEnable=39
ItemDesc=MSI-X PBA Offset and PBA BIR
ItemPointerOffset=3

[Item_40]
ItemUnitOffset=0
ItemUnitNum=1
ItemBitEnable=40
ItemDesc=PCI Express Capability ID
ItemPointerOffset=4

[Item_41]
ItemUnitOffset=1
ItemUnitNum=1
ItemBitEnable=41
ItemDesc=Capabilities Pointer
ItemPointerOffset=4
ItemPointer=5

[Item_42]
ItemUnitOffset=2
ItemUnitNum=2
ItemBitEnable=42
ItemDesc=PCI Express Capabilities
ItemPointerOffset=4

[Item_43]
ItemUnitOffset=4
ItemUnitNum=4
ItemBitEnable=43
ItemDesc=PCI Express Device Capabilities
ItemPointerOffset=4

[Item_44]
ItemUnitOffset=8
ItemUnitNum=2
ItemBitEnable=44
ItemDesc=PCI Express Device Control
ItemPointerOffset=4

[Item_45]
ItemUnitOffset=10
ItemUnitNum=2
ItemBitEnable=45
ItemDesc=PCI Express Device Status
ItemPointerOffset=4

[Item_46]
ItemUnitOffset=12
ItemUnitNum=4
ItemBitEnable=46
ItemDesc=PCI Express Link Capabilities
ItemPointerOffset=4

[Item_47]
ItemUnitOffset=16
ItemUnitNum=2
ItemBitEnable=47
ItemDesc=PCI Express Link Control
ItemPointerOffset=4

[Item_48]
ItemUnitOffset=18
ItemUnitNum=2
ItemBitEnable=48
ItemDesc=PCI Express Link Status
ItemPointerOffset=4

[Item_49]
ItemUnitOffset=36
ItemUnitNum=4
ItemBitEnable=49
ItemDesc=PCI Express Device Capabilities 2
ItemPointerOffset=4

[Item_50]
ItemUnitOffset=40
ItemUnitNum=2
ItemBitEnable=50
ItemDesc=PCI Express Device Control 2
ItemPointerOffset=4

[Item_51]
ItemUnitOffset=0
ItemUnitNum=4
ItemBitEnable=51
ItemDesc=AER Capability ID
ItemPointerOffset=5

[Item_52]
ItemUnitOffset=4
ItemUnitNum=4
ItemBitEnable=52
ItemDesc=AER Uncorrectable Error Status Register
ItemPointerOffset=5

[Item_53]
ItemUnitOffset=8
ItemUnitNum=4
ItemBitEnable=53
ItemDesc=AER Uncorrectable Error Mask Register
ItemPointerOffset=5

[Item_54]
ItemUnitOffset=12
ItemUnitNum=4
ItemBitEnable=54
ItemDesc=AER Uncorrectable Error Severity Register
ItemPointerOffset=5

[Item_55]
ItemUnitOffset=16
ItemUnitNum=4
ItemBitEnable=55
ItemDesc=AER Correctable Error Status Register
ItemPointerOffset=5

[Item_56]
ItemUnitOffset=20
ItemUnitNum=4
ItemBitEnable=56
ItemDesc=AER Correctable Error Mask Register
ItemPointerOffset=5

[Item_57]
ItemUnitOffset=24
ItemUnitNum=4
ItemBitEnable=57
ItemDesc=AER Advanced Error Capabilities and Control Reg.
ItemPointerOffset=5

[Item_58]
ItemUnitOffset=28
ItemUnitNum=8
ItemBitEnable=58
ItemDesc=AER Header Log Register L
ItemPointerOffset=5

[Item_59]
ItemUnitOffset=36
ItemUnitNum=8
ItemBitEnable=59
ItemDesc=AER Header Log Register H
ItemPointerOffset=5

[Item_60]
ItemUnitOffset=56
ItemUnitNum=8
ItemBitEnable=60
ItemDesc=AER TLP Prefix Log Register (Optional) L
ItemPointerOffset=5

[Item_61]
ItemUnitOffset=64
ItemUnitNum=8
ItemBitEnable=61
ItemDesc=AER TLP Prefix Log Register (Optional) H
ItemPointerOffset=5
